Nonvolatile memory devices including multiple charge trapping layers

ABSTRACT

A charge trap nonvolatile memory device includes a gate electrode on a substrate; a charge trapping layer between the substrate and the gate electrode; a charge tunneling layer between the charge trapping layer and the substrate; and a charge blocking layer between the gate electrode and the charge trapping layer. The charge trapping layer includes a first charge trapping layer having a first energy band gap and a second charge trapping layer having a second energy band gap that is different than the first energy band gap. The first and second charge trapping layers are repeatedly stacked and the first and second energy band gaps are smaller than energy band gaps of the charge tunneling layer and the charge blocking layer.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. §119 of Korean Patent Application No. 10-2008-0114593, filed on Nov. 18, 2008, the entire contents of which are herein incorporated by reference in their entirety.

BACKGROUND

Various embodiments disclosed herein relate to nonvolatile memory devices, and more particularly, to a charge trap type of nonvolatile memory devices.

Generally, nonvolatile memory devices can electrically erase and program data and can retain their stored data even when their power supplies are interrupted. Thus, nonvolatile memory devices are used in various fields.

Nonvolatile memory devices may be classified into floating gate type of nonvolatile memory devices and charge trap type of nonvolatile memory devices according to a kind of a memory storage layer constituting a unit cell. A charge trap type of nonvolatile memory devices can realize low power, low voltage and/or high integration.

A charge trap type of a nonvolatile memory device includes a charge trapping layer for injecting and storing charges, a charge tunneling layer and a charge blocking layer. Storing charges in the trapping layer can be performed using a difference of an energy band gap on each layer.

Also, a charge trap type of a nonvolatile memory device can be classified into a single level cell (SLC) storing one bit in one cell and a multi level cell (MLC) storing a plurality of bits in one cell.

SUMMARY

Nonvolatile memory devices according to various embodiments may include a gate electrode on a substrate; a charge trapping layer between the substrate and the gate electrode; a charge tunneling layer between the charge trapping layer and the substrate; and a charge blocking layer between the gate electrode and the charge trapping layer. The charge trapping layer comprises a first charge trapping layer having a first energy band gap and a second charge trapping layer having a second energy band gap that is different than the first energy band gap. The first and second charge trapping layers are repeatedly stacked, and the first and second energy band gaps are smaller than energy band gaps of the charge tunneling layer and the charge blocking layer.

Nonvolatile memory devices according to other embodiments include a substrate, a gate electrode that is spaced apart from the substrate, and a charge tunneling layer, a charge blocking layer and a plurality of alternating first and second charge trapping layers, all of which are stacked between the substrate and the gate electrode. The first and second charge trapping layers have different energy band gaps therebetween that are also less than energy band gaps of both the charge tunneling layer and the charge blocking layer.

Yet other embodiments provide nonvolatile memory devices that also include a substrate, a gate electrode that is spaced apart from the substrate, and a charge tunneling layer, a charge blocking layer and a plurality of alternating first and second charge trapping layers, all of which are stacked between the substrate and the gate electrode. In these embodiments, the first and second charge trapping layers have different composition stoichiometries therebetween that are also different than that of both the charge tunneling layer and the charge blocking layer. As used herein, the term “composition stoichiometry” means the atomic makeup of a molecule. Thus, for example, two layers of silicon oxynitride that have different relative amounts of silicon, oxygen and nitrogen therebetween have different composition stoichiometries and two different compounds, such as silicon nitride and silicon dioxide also have different composition stoichiometries.

BRIEF DESCRIPTION OF THE FIGURES

The accompanying figures are included to provide a further understanding of embodiments of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate various embodiments of the inventive concept and, together with the description, serve to explain principles of embodiments of the inventive concept. In the figures:

FIG. 1 is a top plan view of a nonvolatile memory device in accordance with embodiments of the inventive concept.

FIG. 2 is a perspective view of a nonvolatile memory device in accordance with embodiments of the inventive concept.

FIG. 3 is a cross-sectional view of a nonvolatile memory device in accordance with embodiments of the inventive concept taken along the line I-I′ of FIGS. 1 and 2.

FIG. 4 is a drawing illustrating a charge trapping layer included in a nonvolatile memory device in accordance with embodiments of the inventive concept.

FIG. 5 is an energy band diagram during a program operation in a nonvolatile memory device in accordance with embodiments of the inventive concept.

FIG. 6 is an energy band diagram of a charge maintaining state in a nonvolatile memory device in accordance with embodiments of the inventive concept.

FIGS. 7A and 7B are drawings illustrating whether nonvolatile memory devices for testing a characteristic of HTS (high temperature stability) store charges or not.

FIG. 8 is a graph illustrating characteristics of HTS of a nonvolatile memory device in accordance with embodiments of the inventive concept and a nonvolatile memory device in accordance with a conventional technique.

FIG. 9 is a schematic view of a memory system including a nonvolatile memory device in accordance with embodiments of the inventive concept.

FIG. 10 is a block diagram depicting an example of a memory card including a flash memory device.

FIG. 11 is a block diagram illustrating a data processing system fitted with a flash memory system in accordance with embodiments of the inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various embodiments of the inventive concept now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout.

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items and may be abbreviated as “/”.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first region/layer could be termed a second region/layer, and, similarly, a second region/layer could be termed a first region/layer without departing from the teachings of the disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Embodiments of the inventive concept may be described with reference to top plan and cross-sectional illustrations, which are schematic illustrations of idealized embodiments of the inventive concept. As such, variations from the shapes of the illustrations, as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the inventive concept should not be construed as limited to the particular shapes of regions illustrated herein, but are to include deviations in shapes that result from, e.g., manufacturing. For example, a region illustrated as a rectangle may have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and are not intended to limit the scope of the inventive concept.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present application, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “onto” another element, it may lie directly on the other element or intervening elements or layers may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Like reference numerals refer to like elements throughout the specification.

Spatially relatively terms, such as “beneath,” “below,” “above,” “upper,” “top,” “bottom” and the like, may be used to describe an element and/or feature's relationship to another element(s) and/or feature(s) as, for example, illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and/or operation in addition to the orientation depicted in the figures. For example, when the device in the figures is turned over, elements described as below and/or beneath other elements or features would then be oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. As used herein, “height” refers to a direction that is generally orthogonal to the faces of a substrate.

FIG. 1 is a top plan view of a nonvolatile memory device in accordance with embodiments of the inventive concept. FIG. 2 is a perspective view of a nonvolatile memory device in accordance with embodiments of the inventive concept. FIG. 3 is a cross-sectional view of a nonvolatile memory device in accordance with embodiments of the inventive concept taken along the line I-I′ of FIGS. 1 and 2. FIG. 4 is a drawing illustrating a charge trapping layer included in a nonvolatile memory device in accordance with embodiments of the inventive concept.

Referring to FIGS. 1 through 3, a substrate 100 including active regions defined by a device isolation layer 102 is provided. The active regions include a channel region 104 and source/drain regions 160.

The substrate 100 may be a bulk silicon substrate, a SOI (silicon-on-insulator) substrate, a germanium substrate, a GOI (germanium on insulator) substrate, a silicon-germanium substrate or a substrate of an epitaxial thin film obtained by performing a SEC (selective epitaxial growth) and/or any other microelectronic substrate.

The device isolation layer 102 may be an insulating layer buried in a trench formed in the substrate 100 and may have a plane structure of a line shape. Since the device isolation layers 102 are spaced a predetermined distance apart from each other, the active regions of a line pattern can be defined.

A trap structure 140 is formed on the substrate 100 in which the active regions are defined. The trap structure 140 may include a charge tunneling layer 110, a charge trapping layer 120 and a charge blocking layer 130 that are sequentially stacked on the substrate 100. The trap structure 140 may extend in upper portions of the active regions and the device isolation layers and may be locally formed on an upper portion of each active region.

The charge tunneling layer 110 is a layer through which charges can tunnel when a high electric field is applied between a gate electrode 150 and the substrate 100. For example, the charge tunneling layer 110 may comprise a silicon oxide layer (SiO₂) and/or a silicon oxynitride layer (SiON). The charge tunneling layer 110 may also comprise a high dielectric material such as Al₂O₃, HfO₂, ZrO₂, La₂O₃, Ta₂O₃, TiO₂, SrTiO₃(STO), (Ba,Sr)TiO₃(BST) or a multilayer stacked with combinations thereof.

The charge tunneling layer 110 may be formed by means of a thermal oxidation, a CVD (chemical vapor deposition) process and/or an ALD (atomic layer deposition) process and may have a thickness of about 10 Å to 100 Å.

The charge trapping layer 120 includes a plurality of first and second charge trapping layers (122, 124 of FIG. 4) and charges tunneled from the substrate 100 are trapped in the charge trapping layer 120. The charge trapping layer 120 has, as depicted in FIG. 4, a laminate structure on which the first and second charge trapping layers 122 and 124 are alternately and repeatedly stacked. That is, the first and second charge trapping layers 122 and 124 of at least two layers are provided between the charge tunneling layer 110 and the charge blocking layer 130.

Also, the first and second charge trapping layers 122 and 124 may be sequentially and repeatedly stacked on the charge tunneling layer 110. In some embodiments of the inventive concept, the first and second charge trapping layers 122 and 124 may have the same number (e.g., n number) of layers respectively. Thus, a top surface of the charge tunneling layer 110 is in contact with the first charge trapping layer 122 and a bottom surface of the charge blocking layer 130 may be in contact with the second charge trapping layer 124. Alternatively, both the charge tunneling layer 110 and the charge blocking layer 130 may be in contact with the first charge trapping layer 122 or the second charge trapping layer 124. In other embodiments, the first and second charge trapping layers 122 and 124 may have different numbers of layers from each other.

Here, the first charge trapping layers 122 are formed of material having a first energy band gap and the second charge trapping layers 124 are formed of material having a second energy band gap that is different from, and in some embodiments greater than, the first energy band gap. In some embodiments of the inventive concept, the first charge trapping layers 122 of at least two layers formed between the charge tunneling layer 110 and the charge blocking layer 130 have the same energy level of a conduction band and the same energy level of a valance band. Similarly, the second charge trapping layers 124 of at least two layers also have the same energy level in a conduction band or a valance band. In other embodiments, all the first charge trapping layers 122 have the same band gap and all the second charge trapping layers 124 have the same band gap. In other words, at least two of the first charge trapping layers 122 may have the same energy band gap and at least the two of second charge trapping layers 124 may have the same energy band gap. The first and second charge trapping layers 122 and 124 have an energy band gap smaller than an energy band gap of the charge tunneling layer 110. In other embodiments, at least two of the first and/or second charge trapping layers 122 and 124 have different energy band gaps therebetween.

Alternatively, in other embodiments of the inventive concept, an energy level of a conduction band or a valance band between the first charge trapping layers 122 may become different by controlling nitrogen content. In this case, an energy barrier exists between the first charge trapping layer 122 and the second charge trapping layer 124. For example, the first charge trapping layer 122 may be a silicon nitride layer having an energy band gap of about 4.5 to 5.5 eV and the second charge trapping layer 124 may be a silicon oxynitride layer having an energy band gap of about 5.0 to 7.3 eV. Here, since the second charge trapping layer 124 comprised of a silicon oxynitride layer includes an oxygen atom, the oxygen atom may disturb a movement of trapped charges. Thus, mobility of charges in a silicon oxynitride layer is reduced compared with a silicon nitride layer. That is, in the charge trapping layer 120 extending in adjacent memory cells, at least some charges trapped in the charge trapping layer 120 may be prevented from being laterally diffused into upper portions of the device isolation layer 102 and the source/drain regions 160.

Thus, when retaining charges by trapping charges in the charge trapping layer 120, at least some of the charges can be prevented from horizontally moving and then disappearing. Therefore, a characteristic of charge retention and reliability of a nonvolatile memory device can be improved.

The charge trapping layer 120 may be formed by means of a CVD (chemical vapor deposition) process and/or an ALD (atomic layer deposition) process and may have a thickness of about 10 to 200 Å. More specifically, when the charge trapping layer 120 is formed by means of an ALD (atomic layer deposition), the first and second charge trapping layers 122 and 124 may be formed by controlling a supply time of an oxidizing agent. In some embodiments of the inventive concept, the first and second charge trapping layers 122 and 124 may be deposited to have about the same thickness. In other embodiments of the inventive concept, the first and second charge trapping layers 122 and 124 may be deposited to have a different thickness from each other.

When the charge tunneling layer 110 is formed of a silicon oxynitride layer, an energy band gap of the second trapping layer 124 may become smaller than an energy band gap of the charge tunneling layer 110 by forming an oxygen content of the second charge trapping layer 120 to be smaller than an oxygen content of the charge tunneling layer 110.

Since the first and second charge trapping layers 122 and 124 of a laminate structure are formed between the charge tunneling layer 110 and the charge blocking layer 130, first and second energy band gaps can periodically appear. An energy barrier may be formed at an interface between the first and second charge trapping layers 122 and 124 by a difference of the first and second energy band gaps.

The charge blocking layer 130 insulates the charge trapping layer 120 and the gate electrode 150 and prevents at least some charges from flowing in the charge trapping layer 120 from the gate electrode 150 or in the gate electrode 150 from the charge trapping layer 120. Thus, the charge blocking layer 130 is formed of material having an energy band gap greater than the charge trapping layer 120. The blocking layer 130 may also be formed of material having a dielectric constant higher than the charge tunneling layer 110. That is, the charge blocking layer 130 may have an energy band gap greater than energy band gaps of the charge tunneling layer 110 and the charge trapping layer 120. For example, the charge blocking layer 130 may be formed of a high dielectric material such as Al₂O₃, HfO₂, ZrO₂, La₂O₃, Ta₂O₃, TiO₂, SrTiO₃(STO), (Ba,Sr)TiO₃(BST) or a multilayer stacked with combinations thereof. Accordingly, in some embodiments, the first and second charge trapping layers 122 and 124 have different composition stoichiometries therebetween that are also different than that of both the charge tunneling layer 110 and the charge blocking layer 130.

The gate electrode 150 is formed on the charge blocking layer 130 and may be a line pattern which crosses the active regions. A plurality of gate electrodes 150 are spaced apart from each other on the charge blocking layer 130. The gate electrode 130 may be formed of a single layer comprised of doped polysilicon, metal material such as W, Pt, Ir, conductive metal nitride such as TiN, TaN, WN or conductive metal oxide such as RuO₂. IrO₂ or a multi layer comprised of combinations thereof.

The source/drain regions 160 are formed in the active region of both sides of the gate electrode 150 and a channel region is formed between the source/drain regions 160 by applying a predetermined voltage to the gate electrode 150.

FIG. 5 is an energy band diagram during a program operation in a nonvolatile memory device in accordance with embodiments of the inventive concept.

Referring to FIG. 5, as a voltage for a program operation is applied to the gate electrode, energy bands of the charge tunneling layer 110, the charge trapping layer 120 and the charge blocking layer 130 may be bent due to a difference of electric potential between the gate electrode 150 and the substrate 100. Charges in the substrate 100 are trapped in the charge trapping layer 120 by F-N (Fowler-Nordheim) tunneling.

Charges tunneled in the charge trapping layer 120 may be trapped in the first and second trapping layers 122 and 124 according to energies that the charges have. Since energy band gaps of the first and second charge trapping layers 122 and 124 are different from each other, the probability that the charges tunneled in the charge trapping layer 120 move to the gate electrode 150 is gradually decreased as the charges pass through irregular energy bands. That is, since mobility of charges in the charge trapping layer 120 is decreased, the probability that charges are trapped in the charge trapping layer 120 may be increased.

FIG. 6 is an energy band diagram of a charge maintaining state in a nonvolatile memory device in accordance with embodiments of the inventive concept. Although energy bands of a charge trapping layer are horizontally depicted in FIG. 6, the energy bands of the charge trapping layer may be bent by charges trapped in the charge trapping layer.

Referring to FIGS. 3 and 6, the charge tunneling layer 110, the charge trapping layer 120, the charge blocking layer 130 and the gate electrode 150 may have different energy band gaps from each other and may form an energy barrier according to a difference of energy band gaps.

A first energy barrier (b₁) or a second energy barrier (b₁+b₂) is formed between the charge tunneling layer 110 and the charge trapping layer 120. Here, the first energy barrier (b₁) is a difference of an energy band gap between the charge tunneling layer 110 and the second charge trapping layer 124 and the second energy barrier (b₁+b₂) is a difference of an energy band gap between the charge tunneling layer 110 and the first charge trapping layer 122.

Since the first and second charge trapping layers 122 and 124 having different band gaps from each other are alternately disposed on the charge tunneling layer 110, a plurality of energy barriers may be formed between the charge tunneling layer 110 and the charge blocking layer 130. That is, a third energy barrier (b₂), which is a difference of the first and second energy band gaps, may be formed between the first charge trapping layer 122 and the second charge trapping layer 124. At this time, the third energy barrier (b₂) may be smaller than the first energy barrier (b₁). Since the first and second charge trapping layers 122 and 124 are alternately disposed, the first and second energy band gaps may periodically appear. That is, the third energy barrier (b₂) may be periodically formed between the charge tunneling layer 110 and the charge blocking layer 130. Here, a period that the third energy barriers (b₂) are formed may be different depending on thicknesses of the first and second charge trapping layers 122 and 124.

As the third energy barriers (b₂) are periodically formed between the charge tunneling layer 110 and the charge blocking layer 130, charges in the charge trapping layer 120 have to go over a plurality of the third energy barriers (b₂) so as to move in a direction (i.e., a vertical direction) of the charge blocking layer 130 from the charge tunneling layer 110. Thus, even though charges move in a vertical direction, the probability that the charges tunneled in the charge trapping layer 120 go over the third barriers (b₂) is gradually decreased.

Since the third energy barriers (b₂) are periodically formed in the charge trapping layer 120, at least some charges may be prevented from moving in a direction of the charge blocking layer 130 from the charge tunneling layer 110. Thus, when retaining charges by trapping charges in the charge trapping layer 120, at least some of the charges can be prevented from vertically moving and then disappearing. As described above, since mobility of charges in the second charge trapping layers 120 is decreased, a horizontal movement of at least some trapped charges may be prevented. Thus, a characteristic of charge retention and reliability of a nonvolatile memory device can be improved.

A fourth energy barrier (b₃) is formed between the charge trapping layer 120 and the blocking layer 130. The fourth energy barrier (b₃) may be greater than the first energy barrier (b₁) between the charge tunneling layer 110 and the charge trapping layer 120. The fourth energy barrier (b₃) can prevent at least some charges from tunneling back from the gate electrode 150 to the charge trapping layer 120.

FIGS. 7A and 7B are drawings illustrating whether nonvolatile memory devices for testing a characteristic of HTS store charges or not. FIG. 8 is a graph illustrating characteristics of HTS of a nonvolatile memory device in accordance with embodiments of the inventive concept and a nonvolatile memory device in accordance with a conventional technique.

In FIGS. 7A, 7B and 8, drawing symbols ‘200 a and 200 b’ represent a nonvolatile memory device according to a conventional technique and drawing symbols ‘300 a and 300 b’ represent a nonvolatile memory device according to embodiments of the inventive concept.

In a nonvolatile memory device according to a conventional technique, a charge tunneling layer is formed of a silicon oxide layer (SiO₂), a charge trapping layer is formed of a silicon nitride layer, a charge blocking layer is formed of alumina (Al₂O₃—) and a gate electrode is formed of a tantalum nitride layer (TaN).

In a nonvolatile memory device according to embodiments of the inventive concept, a charge tunneling layer is formed of a silicon oxide layer (SiO₂), a charge trapping layer is formed of a silicon nitride layer (SiN) and a silicon oxynitride layer (SiON) that are repeatedly stacked, a charge blocking layer is formed of alumina (Al₂O₃—) and a gate electrode is formed of a tantalum nitride layer (TaN).

As depicted in FIGS. 7A and 7B, nonvolatile memory devices having memory cells of which charge storage states are different from each other are prepared for a nonvolatile memory device according to a conventional technique and for a nonvolatile memory device according to embodiments of the inventive concept respectively. In FIGS. 7A and 7B, ‘MC1’ represents a memory cell in which a charge is stored and ‘MC2’ represents a memory cell in which a charge is not stored (i.e., erased).

FIG. 7A represents a nonvolatile memory device 200 a and 300 a having memory cells disposed to have a matrix shape in an entire portion of which charges are stored. FIG. 7B represents a nonvolatile memory device 200 b and 300 b having memory cells disposed to have a matrix shape in a portion of which charges are stored. In the nonvolatile memory device 200 b and 300 b of FIG. 7B, charges are not stored in the memory cell (MC2) disposed at one side of the memory cell (MC1) in which charges are stored.

When repeatedly performing a program operation and an erase operation as much as 0 cycle, 1000 cycles and 10000 cycles on nonvolatile memory devices 200 a, 200 b, 300 a and 300 b according to a conventional technique and embodiments of the inventive concept respectively and then baking them for two hours at a temperature of 200° C., a charge loss is calculated from a change (ΔVth) of a threshold voltage being measured. The result is shown in FIG. 8.

When comparing HTS of FIGS. 7A and 7B, a diffusion of a horizontal direction is substantially the same but since a side diffusion of FIG. 7B that charges are not stored in memory cells disposed at one side is great, a difference (ΔVth) of a charge loss in the memory cells of FIGS. 7A and 7B may be a difference of a side diffusion. Thus, a memory device having a small difference of a charge loss may have high reliability.

If comparing the nonvolatile memory devices 200 a and 300 a having memory cells in an entire portion of which charges are stored, it can be appreciated that a charge loss of the nonvolatile memory device 300 a according to embodiments of the inventive concept is smaller than a charge loss of the nonvolatile memory device 200 a of a conventional technique. Also, in a case of a nonvolatile memory device 200 b and 300 b having memory cells in a portion of which charges are stored, it can be appreciated that a charge loss of the nonvolatile memory device 300 b of embodiments of the inventive concept is greatly reduced compared with a charge loss of the nonvolatile memory device 200 b of a conventional technique. That is, in the nonvolatile memory device, it can be appreciated that a side diffusion of charges trapped in a charge trapping layer is greatly reduced. Thus, reliability of a nonvolatile memory device according to embodiments of the inventive concept can be greatly improved compared with the nonvolatile memory device of a conventional technique.

FIG. 9 is a schematic view of a memory system including a nonvolatile memory device in accordance with embodiments of the inventive concept.

Referring to FIG. 9, a memory system 1100 can be applied to a PDA (personal digital assistant), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, a memory card and/or other devices that can transmit and/or receive data in a wireless communication environment.

The memory system 1100 includes a controller 1110, an input/output device 1120 such as a keypad and a display, a memory 1130, an interface 1140 and a bus 1150. The memory 1130 and the interface 1140 communicate with each other through the bus 1150.

The controller 1110 includes at least one microprocessor, at least one digital signal processor, at least one micro controller or other process devices similar to the microprocessor, the digital signal processor and the micro controller. The memory 1130 may be used to store an instruction executed by the controller 1110. The input/output device 1120 can receive data or a signal from the outside of the system 1100 or transmit data or a signal to the outside of the system 1100. For example, the input/output device 1120 may include a keyboard, a keypad and/or a display.

The memory 1130 includes the nonvolatile memory device according to embodiments of the inventive concept. The memory 1130 may further include a different kind of memory, a volatile memory device capable of random access and various kinds of memories.

The interface 1140 transmits data to a communication network or receives data from a communication network.

FIG. 10 is a block diagram depicting an example of a memory card 1200 including a flash memory device.

Referring to FIG. 10, the memory card 1200 for supporting a storage capability of a large capacity is fitted with a flash memory device according to embodiments of the inventive concept. The memory card 1200 according to embodiments of the inventive concept includes a memory controller 1220 controlling every data exchange between a host and the flash memory device 1210.

A SRAM 1221 is used as an operation memory of a processing unit 1222. A host interface 1223 includes data exchange protocols of a host to be connected to the memory card 1200. An error correction block 1224 detects and corrects errors included in data readout from a multi bit flash memory device 1210. A memory interface 1225 interfaces with the flash memory device 1210 of embodiments of the inventive concept. The processing unit 1222 performs control operations for exchanging data of the memory controller 1220. Even though not depicted in drawings. it is apparent to one of ordinary skill in the art that the memory card 1200 according to embodiments of the inventive concept can further include a ROM (not shown) storing code data for interfacing with the host.

In the flash memory device, the memory card, or the memory system, a memory system having high reliability can be provided through the flash memory device 1210 including dummy cells having an improved erasure characteristic. Especially, a flash memory device according to embodiments of the inventive concept can be provided to a memory system such as a SSD (solid state disk) which is recently developed. In this case, a memory system having high reliability can be realized by reducing read errors caused by dummy cells.

FIG. 11 is a block diagram illustrating a data processing system fitted with a flash memory system in accordance with various embodiments of the present invention.

Referring to FIG. 11, a flash memory system 1310 of embodiments of the inventive concept is built in a data processing system such as a mobile product or a desk top computer. The data processing system 1300 according to embodiments of the inventive concept includes the flash memory system 1310 and a modem 1320, a central processing unit 1330, a RAM (random access memory), a user interface 1350 that are electrically connected to a system bus 1360 respectively. The flash memory system 1310 may be constructed so as to be identical to the memory system or the flash memory system described above. The flash memory system 1310 stores data processed by the central processing unit 1330 or data input from an external device. Here, the flash memory system 1310 may be comprised of a SSD (solid state disk) and in this case, the data processing system 1310 can stably store huge amounts of data in the flash memory system 1310. As reliability is improved, the flash memory system 1310 can reduce resources used to correct errors, thereby providing a high speed data exchange function to the data processing system 1300. Even though not depicted in the drawings, it is apparent by one of ordinary skill in the art that the data processing unit 1300 according to embodiments of the inventive concept can further include an application chipset, a camera image processor (CIS) and/or an input/output device.

Flash memory devices or memory systems according to embodiments of the inventive concept can be mounted with various types of packages. For example, a flash memory device or a memory system according to embodiments of the inventive concept can be packaged with methods such as PoP (package on package), ball grid array (BGA), chip scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), die in waffle pack, die in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), thin quad flatpack (TQFP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP), wafer-level processed stack package (WSP) and mounted.

Nonvolatile memory devices according to embodiments of the inventive concept can be embodied as a laminate structure in which first and second charge trapping layers having different energy band gaps from each other are repeatedly stacked and can prevent a horizontal movement and a vertical movement of at least some charges by forming a charge trapping layer. Thus, a loss of charges stored in a charge trapping layer can be reduced, thereby improving a charge retention characteristic of a nonvolatile memory device. Consequently, reliability of a nonvolatile memory device can be improved.

Although a few embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents. Therefore, the above-disclosed subject matter is to be considered illustrative, and not restrictive. 

1. A nonvolatile memory device comprising: a gate electrode on a substrate; a charge trapping layer between the substrate and the gate electrode; a charge tunneling layer between the charge trapping layer and the substrate; and a charge blocking layer between the gate electrode and the charge trapping layer, wherein the charge trapping layer comprises a first charge trapping layer having a first energy band gap and a second charge trapping layer having a second energy band gap that is different than the first energy band gap, the first and second charge trapping layers are repeatedly stacked and the first and second energy band gaps are smaller than energy band gaps of the charge tunneling layer and the charge blocking layer.
 2. The nonvolatile memory device of claim 1, wherein the first and second charge trapping layers are repeatedly stacked at least two times.
 3. The nonvolatile memory device of claim 1, wherein an energy band gap between the charge tunneling layer and the charge blocking layer is formed by periodically repeating the first and second energy band gaps.
 4. The nonvolatile memory device of claim 1, wherein the first and second charge trapping layers between the charge tunneling layer and the charge blocking layer have a same energy level of a conduction band and a same energy level of a valance band.
 5. The nonvolatile memory device of claim 1, wherein the first charge trapping layer comprises a silicon nitride layer and the second charge trapping layer comprises a silicon oxynitride layer.
 6. The nonvolatile memory device of claim 1, wherein the charge tunneling layer is directly on the first charge trapping layer and the charge blocking layer is directly on the second charge trapping layer.
 7. The nonvolatile memory device of claim 1, wherein the first and second charge trapping layers have a thickness ratio of about 1:1.
 8. The nonvolatile memory device of claim 1, wherein the gate electrode comprises a plurality of line patterns and the charge trapping layer extends under the plurality of line patterns.
 9. The nonvolatile memory device of claim 1, wherein the charge blocking layer has an energy band gap greater than the energy band gap of the charge tunneling layer.
 10. A nonvolatile memory device comprising: a substrate; a gate electrode that is spaced apart from the substrate; and a charge tunneling layer, a charge blocking layer and a plurality of alternating first and second charge trapping layers, all of which are stacked between the substrate and the gate electrode, the first and second charge trapping layers having different energy band gaps therebetween that are also less than energy band gaps of both the charge tunneling layer and the charge blocking layer.
 11. The nonvolatile memory device of claim 10 wherein at least two of the first and/or second charge trapping layers also have different energy band gaps therebetween.
 12. The nonvolatile memory device of claim 10 wherein the charge blocking layer has greater energy band gap than the charge tunneling layer.
 13. The nonvolatile memory device of claim 10 wherein the first and second charge trapping layers have different composition stoichiometries therebetween that are also different than that of both the charge tunneling layer and the charge blocking layer.
 14. The nonvolatile memory device of claim 13 wherein the charge tunneling layer comprises silicon dioxide, silicon oxynitride and/or a high dielectric constant material, wherein the charge blocking layer comprises a high dielectric constant material, wherein the first charge trapping layers comprise silicon nitride and wherein the second charge trapping layers comprise silicon oxynitride having different composition stoichiometry than the charge tunneling layer.
 15. A nonvolatile memory device comprising: a substrate; a gate electrode that is spaced apart from the substrate; and a charge tunneling layer, a charge blocking layer and a plurality of alternating first and second charge trapping layers, all of which are stacked between the substrate and the gate electrode, the first and second charge trapping layers having different composition stoichiometries therebetween that are also different than that of both the charge tunneling layer and the charge blocking layer.
 16. The nonvolatile memory device of claim 15 wherein at least two of the first and/or second charge trapping layers also have different composition stoichiometries therebetween.
 17. The nonvolatile memory device of claim 15 wherein the charge tunneling layer comprises silicon dioxide, silicon oxynitride and/or a high dielectric constant material, wherein the charge blocking layer comprises a high dielectric constant material, wherein the first charge trapping layers comprise silicon nitride and wherein the second charge trapping layers comprise silicon oxynitride having different composition stoichiometry than the charge tunneling layer.
 18. The nonvolatile memory device of claim 1 wherein the first charge trapping layers have a same energy level of a conduction band and a same energy level of a valance band and/or the second charge trapping layers have a same energy level of a conduction band and a same energy level of a valence band. 